SELECTIVE ETCHING PROCESS FOR SiGe AND DOPED EPITAXIAL SILICON

ABSTRACT

The present disclosure relates to a fabricating procedure of a radio frequency device, in which a precursor wafer including active layers, SiGe layers, and a silicon handle substrate is firstly provided. Each active layer is formed from doped epitaxial silicon and underneath a corresponding SiGe layer. The silicon handle substrate is over each SiGe layer. Next, the silicon handle substrate is removed completely, and the SiGe layer is removed completely. An etch passivation film is then formed over each active layer. Herein, removing each SiGe layer and forming the etch passivation film over each active layer utilizes a same reactive chemistry combination, which reacts differently to the SiGe layer and the active layer. The reactive chemistry combination is capable of producing a variable performance, which is an etching performance of the SiGe layer or a forming performance of the etch passivation film over the active layer.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.17/389,977, filed Jul. 30, 2021, which claims the benefit of provisionalpatent application Ser. No. 63/157,057, filed Mar. 5, 2021, thedisclosures of which are hereby incorporated herein by reference intheir entireties.

FIELD OF THE DISCLOSURE

The present disclosure relates to a fabricating procedure of a radiofrequency (RF) device, and more particularly to a selective etchingprocess for silicon germanium (SiGe) and doped epitaxial silicon in thefabricating procedure of the radio frequency (RF) device.

BACKGROUND

The wide utilization of cellular and wireless devices drives the rapiddevelopment of radio frequency (RF) technologies. The substrates onwhich RF devices are fabricated play an important role in achieving highlevel performance in the RF technologies. Fabrications of the RF deviceson conventional silicon substrates may benefit from low cost of siliconmaterials, a large-scale capacity of wafer production, well-establishedsemiconductor design tools, and well-established semiconductormanufacturing techniques.

Despite the benefits of using conventional silicon substrates for RFdevice fabrications, it is well known in the industry that conventionalsilicon substrates may have two undesirable properties for RF devices:harmonic distortion and low resistivity values. The harmonic distortionis a critical impediment to achieving high level linearity in the RFdevices built over silicon substrates. In addition, high speed andhigh-performance transistors are more densely integrated in RF devices.Consequently, the amount of heat generated by the RF devices willincrease significantly due to the large number of transistors integratedin the RF devices, the large amount of power passing through thetransistors, and/or the high operation speed of the transistors.Accordingly, it is desirable to package the RF devices in aconfiguration for better heat dissipation.

Radio frequency silicon on insulator (RFSOI) wafers are conventionallyused for fabricating RF devices. However, with the looming shortage ofconventional RFSOI wafers expected in the coming years, alternativetechnologies are being devised to get around the need for highresistivity using silicon wafers, the trap rich layer formation, andSmart-Cut SOI wafer process. One alternative technology is based on theuse of a silicon germanium (SiGe) layer instead of a buried oxide layer(BOX) between a silicon substrate and a silicon epitaxial layer;however, this technology will also suffer from the deleteriousdistortion effects due to the silicon substrate, similar to what isobserved in an RFSOI technology.

In addition, due to the narrow gap nature of the SiGe material, it ispossible that the SiGe between the silicon substrate and the siliconepitaxial layer may be conducting, which may cause appreciable currentleakage. Therefore, in some applications, such as switch field-effecttransistor (FET) applications, the presence of the SiGe layer can causeharm to the devices.

To reduce deleterious harmonic distortion of the RF devices and toutilize the Si—SiGe—Si structure to manufacture RF devices withoutundesirable current leakage in the RF devices, it is therefore an objectof the present disclosure to provide an improved fabricating method forenhancing thermal and electrical performance of the devices.

SUMMARY

The present disclosure relates to a fabricating procedure of a radiofrequency (RF) device, and more particularly to a selective etchingprocess for silicon germanium (SiGe) and doped epitaxial silicon in thefabricating procedure of the radio frequency (RF) device. According toan exemplary fabricating process, a precursor wafer, which includes anumber of device regions, a number of interfacial layers, and a siliconhandle substrate, is firstly provided. Each device region includes anactive layer that is fabricated from doped epitaxial silicon. Eachinterfacial layer formed of silicon germanium (SiGe) is directly overone active layer of a corresponding device region, and the siliconhandle substrate is over each interfacial layer. Next, the siliconhandle substrate is removed completely, and each interfacial layer isremoved completely to expose the active layer. An etch passivation filmis then formed directly over the active layer of each device region.Herein, both removing each interfacial layer and forming the etchpassivation film utilize a same reactive chemistry combination. Thisreactive chemistry combination is chosen in a manner that the reactivechemistry combination reacts differently to the interfacial layer andthe active layer. The reactive chemistry combination is capable ofproducing a variable net performance, which is an etching performance ofthe interfacial layer or a forming performance of the etch passivationfilm over the active layer.

In one embodiment of the exemplary fabricating process, the interfaciallayer is removed by a dry etching process.

In one embodiment of the exemplary fabricating process, the reactivechemistry combination is a mixed gas flow of sulfur hexafluoride (SF₆),nitrogen (N₂), and boron chloride (BCl₃), such that reactive radicalsfluorine (F), chlorine (Cl), boron nitride (BN), and boron chloride(BCl_(x)) are provided in removing the interfacial layer and forming theetch passivation film. The F and Cl radicals are capable of etchingdoped epitaxial silicon and SiGe, and the BN and BCl_(x) radicals arecapable of forming a passivation material on doped epitaxial silicon andSiGe. A competition between an etching rate of the F and Cl radicals anda forming rate of the BN and BCl_(x) radicals determines the netperformance. For the interfacial layer, the etching rate of the F and Clradicals is faster than the forming rate of the BN and BCl_(x), suchthat the net performance is the etching performance leading to theremoval of the interfacial layer. For the active layer, the etching rateof the F and Cl radicals is slower than the forming rate of the BN andBC_(x), such that the net performance is the forming performance of theetch passivation film over the active layer.

In one embodiment of the exemplary fabricating process, in the mixed gasflow, SF₆ has a flow rate between 5 sccm and 60 sccm, N₂ has a flow ratebetween 20 sccm and 90 sccm, and BCl₃ has a flow rate between 20 sccmand 90 sccm.

In one embodiment of the exemplary fabricating process, the flow rate ofSF₆, the flow rate of N₂, and the flow rate of BCl₃ are constant inremoving the interfacial layer and forming the etch passivation film.

In one embodiment of the exemplary fabricating process, an oxygen (O₂)gas flow and an argon (Ar) gas flow are used with the reactive chemistrycombination in removing the interfacial layer and forming the etchpassivation film.

In one embodiment of the exemplary fabricating process, the O₂ gas flowhas a flow rate between 50 sccm and 400 sccm, and the Ar gas flow has aflow rate between 10 sccm and 60 sccm.

According to another embodiment, the exemplary fabricating processfurther includes a breakthrough etching step before the removal of theinterfacial layer. The breakthrough etching step removes a surface oxidelayer, which is formed after the removal of the silicon handle substrateand directly on the interfacial layer, to expose the interfacial layer.

In one embodiment of the exemplary fabricating process, the surfaceoxide layer is removed by a dry etching process, and is pre-calibrated.

In one embodiment of the exemplary fabricating process, the surfaceoxide layer is removed using an SF6 gas flow.

In one embodiment of the exemplary fabricating process, during thebreakthrough etching step, the SF₆ gas flow has a flow rate between 5sccm and 40 sccm.

In one embodiment of the exemplary fabricating process, an O₂ gas flowand an Ar gas flow are used with the SF₆ gas flow in the breakthroughetching step, where the O₂ gas flow has a flow rate between 50 sccm and400 sccm, and the Ar gas flow has a flow rate between 10 sccm and 60sccm.

In one embodiment of the exemplary fabricating process, the surfaceoxide layer and the interfacial layer are removed by a same dry etchingprocess but utilize different reactive chemistry combinations.

In another aspect, any of the foregoing aspects individually ortogether, and/or various separate aspects and features as describedherein, may be combined for additional advantage. Any of the variousfeatures and elements as disclosed herein may be combined with one ormore other disclosed features and elements unless indicated to thecontrary herein.

Those skilled in the art will appreciate the scope of the presentdisclosure and realize additional aspects thereof after reading thefollowing detailed description of the preferred embodiments inassociation with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part ofthis specification illustrate several aspects of the disclosure, andtogether with the description serve to explain the principles of thedisclosure.

FIG. 1 shows an exemplary radio frequency (RF) device with enhancedthermal and electrical performance according to one embodiment of thepresent disclosure.

FIG. 2 provides a flow diagram that illustrates an exemplary fabricatingprocedure of the RF device shown in FIG. 1 according to one embodimentof the present disclosure.

FIGS. 3-14 illustrate the steps associated with the fabricatingprocedure provided in FIG. 2 .

It will be understood that for clear illustrations, FIGS. 1-14 may notbe drawn to scale.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information toenable those skilled in the art to practice the embodiments andillustrate the best mode of practicing the embodiments. Upon reading thefollowing description in light of the accompanying drawing figures,those skilled in the art will understand the concepts of the disclosureand will recognize applications of these concepts not particularlyaddressed herein. It should be understood that these concepts andapplications fall within the scope of the disclosure and theaccompanying claims.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present disclosure. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will be understood that when an element such as a layer, region, orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present.Likewise, it will be understood that when an element such as a layer,region, or substrate is referred to as being “over” or extending “over”another element, it can be directly over or extend directly over theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly over” or extending“directly over” another element, there are no intervening elementspresent. It will also be understood that when an element is referred toas being “connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or“horizontal” or “vertical” may be used herein to describe a relationshipof one element, layer, or region to another element, layer, or region asillustrated in the Figures. It will be understood that these terms andthose discussed above are intended to encompass different orientationsof the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes,” and/or “including” when used herein specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to schematicillustrations of embodiments of the disclosure. As such, the actualdimensions of the layers and elements can be different, and variationsfrom the shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are expected. For example, aregion illustrated or described as square or rectangular can haverounded or curved features, and regions shown as straight lines may havesome irregularity. Thus, the regions illustrated in the figures areschematic and their shapes are not intended to illustrate the preciseshape of a region of a device and are not intended to limit the scope ofthe disclosure. Additionally, sizes of structures or regions may beexaggerated relative to other structures or regions for illustrativepurposes and, thus, are provided to illustrate the general structures ofthe present subject matter and may or may not be drawn to scale. Commonelements between figures may be shown herein with common element numbersand may not be subsequently re-described.

FIG. 1 shows an exemplary RF device 10 formed from a silicon handlesubstrate-silicon germanium interfacial layer-silicon epitaxial layer(Si—SiGe—Si) wafer (processing details are described in followingparagraphs) according to one embodiment of the present disclosure. Forthe purpose of this illustration, the exemplary RF device 10 includes amold device die 12 with a device region 14, device passivation layers15, and a first mold compound 16, and a multilayer redistributionstructure 18 formed under the mold device die 12.

In detail, the device region 14 includes a front-end-of-line (FEOL)portion 20 and a back-end-of-line (BEOL) portion 22 underneath the FEOLportion 20. In one embodiment, the FEOL portion 20 is configured toprovide a switch field-effect transistor (FET), and includes an activelayer 24 and a contact layer 26. Herein, the active layer 24 has asource 28 (e.g., N+ doped silicon), a drain 30 (e.g., N+ doped silicon),and a channel 32 (e.g., P doped silicon) between the source 28 and thedrain 30. The source 28, the drain 30, and the channel 32 are formedfrom a same silicon epitaxial layer. The contact layer 26 is formedunderneath the active layer 24 and includes a gate structure 34, asource contact 36, a drain contact 38, and a gate contact 40. The gatestructure 34 may be formed of silicon oxide, and extends horizontallyunderneath the channel 32 (from underneath the source 28 to underneaththe drain 30). The source contact 36 is connected to and under thesource 28, the drain contact 38 is connected to and under the drain 30,and the gate contact 40 is connected to and under the gate structure 34.An insulating material 42 may be formed around the source contact 36,the drain contact 38, the gate structure 34, and the gate contact 40 toelectrically separate the source 28, the drain 30, and the gatestructure 34. In different applications, the FEOL portion 20 may havedifferent FET configurations or provide different device components,such as a diode, a capacitor, a resistor, and/or an inductor.

In addition, the FEOL portion 20 also includes isolation sections 44,which reside over the insulating material 42 of the contact layer 26 andsurround the active layer 24. The isolation sections 44, which may beformed of silicon dioxide, are configured to electrically separate theRF device 10, especially the active layer 24, from other devices formedin a common wafer (not shown). Herein, the isolation sections 44 mayextend from a top surface of the contact layer 26 and vertically beyonda top surface of the active layer 24 to define an opening 46 that iswithin the isolation sections 44 and over the active layer 24.

Notice that the active layer 24 is formed from a silicon epitaxial layerof the Si—SiGe—Si wafer, while the silicon handle substrate and SiGeinterfacial layer of the Si—SiGe—Si wafer are completely removed duringthe fabricating process of the RF device 10 (process details aredescribed in following paragraphs).

In one embodiment, the device passivation layers 15 include a firstdevice passivation layer 15-1 and a second device passivation layer15-2. The first device passivation layer 15-1 extends over an entirebackside of the device region 14, such that the first device passivationlayer 15-1 continuously covers exposed surfaces within the opening 46and top surfaces of the isolation sections 44. The first devicepassivation layer 15-1 may be formed of silicon dioxide and isconfigured to terminate the surface bonds at the top surface of theactive layer 24, which may be responsible for unwanted leakage. Thesecond device passivation layer 15-2 is formed directly over the firstdevice passivation layer 15-1. Herein, the second device passivationlayer 15-2 may be formed of silicon nitride and is configured to providean excellent barrier to moisture and impurities, which could diffuseinto the channel 32 of the active layer 24 and cause reliabilityconcerns in the device.

The RF device 10 further includes an etch passivation film 48, which maybe formed of boron nitride (BN) and boron chloride (BCl_(x), x=0-3),directly over the top surface of the active layer 24 and within theopening 46. As such, the first device passivation layer 15-1 is directlyover the etch passivation film 48. The etch passivation film 48 isformed as a result of a selective etching process and protects theactive layer 24 from being further etched (process details are describedin following paragraphs).

The first mold compound 16 is formed over the device passivation layers15, such that the first mold compound 16 fills the opening 46 and is incontact with the second device passivation layer 15-2. The first moldcompound 16 may have a thermal conductivity greater than 1 W/m·K, orgreater than 10 W/m·K. In addition, the first mold compound 16 may havea low dielectric constant less than 8, or between 3 and 5 to yield lowRF coupling. In one embodiment, the first mold compound 16 may be formedof thermoplastics or thermoset polymer materials, such as PPS (polyphenyl sulfide), overmold epoxies doped with boron nitride, alumina,carbon nanotubes, or diamond-like thermal additives, or the like. Athickness of the first mold compound 16 is based on the required thermalperformance of the RF device 10, the device layout, the distance fromthe multilayer redistribution structure 18, as well as the specifics ofthe package and assembly. The first mold compound 16 may have athickness between 200 μm and 500 μm. Notice that silicon crystal, whichhas no nitrogen or oxygen content, does not exist between the first moldcompound 16 and the top surface of the active layer 24. Each of thedevice passivation layers 15 is formed of silicon composite.

The BEOL portion 22 is underneath the FEOL portion 20 and includesmultiple connecting layers 50 formed within dielectric layers 52. Someof the connecting layers 50 are encapsulated by the dielectric layers 52(not shown), while some of the connecting layers 50 have a bottomportion not covered by the dielectric layers 52. Certain connectinglayers 50 are electrically connected to the FEOL portion 20. For thepurpose of this illustration, one of the connecting layers is connectedto the source contact 36, and another connecting layer 50 is connectedto the drain contact 38.

The multilayer redistribution structure 18, which is formed underneaththe BEOL portion 22 of the mold device die 12, includes a number ofredistribution interconnections 54, a dielectric pattern 56, and anumber of bump structures 58. Herein, each redistributioninterconnection 54 is connected to a corresponding connecting layer 50within the BEOL portion 22 and extends over a bottom surface of the BEOLportion 22. The connections between the redistribution interconnections54 and the connecting layers 50 are solder-free. The dielectric pattern56 is formed around and underneath each redistribution interconnection54. A bottom portion of each redistribution interconnection 54 isexposed through the dielectric pattern 56. Each bump structure 58 isformed at a bottom of the multilayer redistribution structure 18 andelectrically coupled to a corresponding redistribution interconnection54 through the dielectric pattern 56. Consequently, the redistributioninterconnections 54 are configured to connect the bump structures 58 tocertain ones of the connecting layer 50 in the BEOL portion 22, whichare electrically connected to the FEOL portion 20. As such, the bumpstructures 58 are electrically connected to the FEOL portion 20 viacorresponding redistribution interconnections 54 and correspondingconnecting layers 50. In addition, the bump structures 58 are separatefrom each other and extend underneath the dielectric pattern 56.

The multilayer redistribution structure 18 may be free of glass fiber orglass-free. Herein, the glass fiber refers to individual glass strandstwisted to become a larger grouping. These glass strands may then bewoven into a fabric. The redistribution interconnections 54 may beformed of copper or other suitable metals. The dielectric pattern 56 maybe formed of benzocyclobutene (BCB), polyimide, or other dielectricmaterials. The bump structures 58 may be solder balls or copper pillars.The multilayer redistribution structure 18 has a thickness between 2 μmand 300 μm.

FIG. 2 provides a flow diagram that illustrates an exemplary fabricatingprocedure 200 of the RF device 10 shown in FIG. 1 according to oneembodiment of the present disclosure. FIGS. 3-14 illustrate the stepsassociated with the fabricating procedure 200 provided in FIG. 2 .Although the exemplary steps are illustrated in a series, the exemplarysteps are not necessarily order dependent. Some steps may be done in adifferent order than that presented. Further, processes within the scopeof this disclosure may include fewer or more steps than thoseillustrated in FIGS. 3-14 .

Initially, a Si—SiGe—Si wafer 62 is provided as illustrated in FIG. 3(Step 202). The Si—SiGe—Si wafer 62 includes a common silicon epitaxiallayer 64, a common SiGe interfacial layer 66 over the common siliconepitaxial layer 64, and a silicon handle substrate 68 over the commonSiGe interfacial layer 66. Herein, the common silicon epitaxial layer 64is formed from a device grade silicon material, which has desiredsilicon epitaxial characteristics to form electronic devices. The commonSiGe interfacial layer 66, which separates the common silicon epitaxiallayer 64 from the silicon handle substrate 68, is formed from an alloywith any molar ratio of Si and Ge. The higher the Ge concentration, thebetter the etching selectivity between the silicon handle substrate 68and the common SiGe interfacial layer 66 and between the common SiGeinterfacial layer 66 and the common silicon epitaxial layer 64. However,the higher the Ge concentration, the more difficult the epitaxial growthof the common silicon epitaxial layer 64 becomes. In one embodiment, thecommon SiGe interfacial layer 66 may have a Ge concentration between 25%and 30%. The Ge concentration may be uniform throughout the common SiGeinterfacial layer 66 or may be vertically graded so as to yield thenecessary strain relief for the growth of the common silicon epitaxiallayer 64. The silicon handle substrate 68 may consist of conventionallow cost, low resistivity, and high dielectric constant silicon. Thecommon silicon epitaxial layer 64 has higher resistivity, lower harmonicgeneration, and lower dielectric constant than the silicon handlesubstrate 68. A thickness of the common silicon epitaxial layer 64 maybe between 700 nm and 2000 nm, a thickness of the common SiGeinterfacial layer 66 may be between 100 nm and 1000 nm, and a thicknessof the silicon handle substrate 68 may be between 200 μm and 500 μm.

Next, a complementary metal-oxide-semiconductor (CMOS) process isperformed on the Si—SiGe—Si wafer 62 to provide a precursor wafer 70with a number of device regions 14, as illustrated in FIG. 4 (Step 204).For the purpose of this illustration, the FEOL portion 20 of each deviceregion 14 is configured to provide a switch FET. In differentapplications, the FEOL portion 20 may have different FET configurationsor provide different device components, such as a diode, a capacitor, aresistor, and/or an inductor.

In this embodiment, the isolation sections 44 of each device region 14extend through the common silicon epitaxial layer 64 and the common SiGeinterfacial layer 66 and extend into the silicon handle substrate 68. Assuch, the common SiGe interfacial layer 66 separates into a number ofindividual SiGe interfacial layers 66 l, and the common siliconepitaxial layer 64 separates into a number of individual siliconepitaxial layers 64 l, each of which is used to form a correspondingactive layer 24 (i.e., a doped source-drain epitaxial silicon layer) inone device region 14. The isolation sections 44 may be formed by shallowtrench isolation (STI).

The top surface of the active layer 24 is in contact with acorresponding SiGe interfacial layer 66 l. The silicon handle substrate68 resides over each SiGe interfacial layer 66 l, and portions of thesilicon handle substrate 68 may reside over the isolation sections 44.The BEOL portion 22 of the device region 14, which includes at least themultiple connecting layers 50 and the dielectric layers 52, is formedunder the contact layer 26 of the FEOL portion 20. Bottom portions ofcertain connecting layers 50 are exposed through the dielectric layers52 at the bottom surface of the BEOL portion 22.

After the precursor wafer 70 is completed, the precursor wafer 70 isthen bonded to a temporary carrier 72, as illustrated in FIG. 5 (Step206). The precursor wafer 70 may be bonded to the temporary carrier 72via a bonding layer 74, which provides a planarized surface to thetemporary carrier 72. The temporary carrier 72 may be a thick siliconwafer from a cost and thermal expansion point of view, but may also beconstrued of glass, sapphire, or other suitable carrier material. Thebonding layer 74 may be a span-on polymeric adhesive film, such as theBrewer Science WaferBOND line of temporary adhesive materials.

The silicon handle substrate 68 is then selectively removed to providean etched wafer 76, wherein the selective removal is stopped on eachSiGe interfacial layer 66 l, as illustrated in FIG. 6 (Step 208).Removing the silicon handle substrate 68 may be provided by chemicalmechanical grinding and an etching process with a wet/dry etchantchemistry, which may be potassium hydroxide (KOH), sodium hydroxide(NaOH), acetylcholine (ACH), tetramethylammonium hydroxide (TMAH), orxenon difluoride (XeF2), or provided by the etching process itself. Asan example, the silicon handle substrate 68 may be ground to a thinnerthickness to reduce the following etching time. An etching process isthen performed to completely remove the remaining silicon handlesubstrate 68.

Since the silicon handle substrate 68 and the SiGe interfacial layers 66l have different ingredients/characteristics, they will have differentreactions to a same etching technique. For instance, the SiGeinterfacial layers 66 l have a much slower etching speed than thesilicon handle substrate 68 with a same etchant (e.g., TMAH, KOH, NaOH,ACH, or XeF2). Consequently, the etching system is capable ofidentifying the presence of the SiGe interfacial layers 66 l and capableof indicating when to stop the etching process. Herein each SiGeinterfacial layer 66 l functions as an etch stop layer for thecorresponding active layer 24 (i.e., the doped source-drain epitaxialsilicon layer).

In addition, the isolation sections 44 may be formed of silicon dioxide,which may resist etching chemistries such as TMAH, KOH, NaOH, ACH, orXeF2. During the removal process, the isolation sections 44 are hardlyremoved and protect sides of each active layer 24. If the isolationsections 44 extend vertically beyond the SiGe interfacial layers 66 l,the removal of the silicon handle substrate 68 will provide the opening46 over each active layer 24 and within the isolation sections 44. Thebonding layer 74 and the temporary carrier 72 protect the bottom surfaceof each BEOL portion 22.

Due to the narrow gap nature of the SiGe material, it is possible thatthe SiGe interfacial layers 66 l may be conducting. Each SiGeinterfacial layer 66 l may cause appreciable leakage between the source28 and the drain 30 of the active layer 24. Therefore, in someapplications, especially FET applications, it is desired to completelyremove the SiGe interfacial layers 66 l.

After the removal of the silicon handle substrate 68, there might be asurface oxide layer (i.e., silicon oxide layer) 67 formed on each SiGeinterfacial layer 66 l because the SiGe interfacial layer 66 l isexposed to the atmosphere. Accordingly, before removing the SiGeinterfacial layers 66 l, there is a breakthrough etching step to removeeach surface oxide layer 67 on the SiGe interfacial layers 66 l, asillustrated in FIG. 7 (Step 210).

The surface oxide layer 67 may be removed by a dry etching processutilizing a plasma etch system with a sulfur hexafluoride (SF₆) gasflow. Herein, the SF_(6 gas) flow may be provided with an argon (Ar) gasflow and an oxygen (O₂) gas flow, where the Ar gas flow acts as acarrier gas flow, and the O₂ gas flow is used to dilute the SF₆ gas flowand implement uniformity during the processing. In this breakthroughetching step, the SF₆ gas flow has a flow rate of 5-60 standard cubiccentimeter per minute (sccm), the O₂ gas flow has a flow rate of sccm,and the Ar gas flow has a flow rate of 10-60 sccm. Since the surfaceoxide layer 67 is typically very thin (e.g., about a few Å), a durationof the breakthrough etching step is very short and can be pre-calibratedin the plasma etch system (e.g., by using a timer). The isolationsections 44 formed of silicon dioxide may only be minimally etched inthis breakthrough etching step (Step 210) and still protect sides ofeach active layer 24.

As described above, each active layer 24 is directly underneath the SiGeinterfacial layer 66 l that may cause unwanted current leakage in theactive layer 24. It is therefore highly desired to completely removeeach SiGe interfacial layer 66 l without harming the active layer 24.The SiGe interfacial layers 66 l may be removed by the same dry etchingprocess used to remove the surface oxide layer 67 in the same plasmaetch system, but by utilizing a different reactive chemistrycombination. The reactive chemistry combination provides the removal ofthe SiGe interfacial layers 66 l followed by the etch passivation film48 formed on the surface of the minimally etched active layer 24.

Table 1 shows detailed conditions of the dry etching process in thebreakthrough etching step (Step 210), a SiGe etching step (Step 212),and a passivation film forming step (Step 214). In the SiGe etching stepand the passivation film forming step, the reactive chemistrycombination is a mixed gas flow of SF₆, Nitrogen (N₂), and boronchloride (BCl₃). These reactive gas components may be carried by the Argas flow and may be diluted to various concentration degrees by usingthe O₂ gas flow. Note that the reactions of the Ar and O₂ gas flows arenegligible during Steps 210-214. The following reactions are expected tooccur in the plasma etch system once power is applied:

SF₆=>F*+SF_(x)

BCl₃=>BCl_(y)+Cl*

BCl_(y)+N₂=>BN+BCl_(y)+Cl*

Various reactive radicals fluorine (F), chlorine (Cl), BN, and boronchloride (BCl_(y)) are generated, wherein * represents an excited stateof the radicals (with high energy), x represents a number between 0 and6, and y represents a number between 0 and 3. Herein, the F and Clradicals can etch silicon and SiGe, while the BN and BCl_(x) radicalscan form an etch passivation film. A competition between the etchingrate of the F and Cl radicals and the forming rate of the BN and BCl_(x)radicals determines a net performance, which can lead to an SiGe etchingresult or a passivation film forming result.

TABLE 1 Break- through SiGe Etching Step Process Etching and Passivationparameter Units Step Film Forming Step Wafer Celsius  15-50  15-50Temperature Power Watt 400-1400 400-1400 Bias Watt  0-200  0-200Pressure milliTorr  05-60  05-60 SF₆ sccm (standard cubic  05-40  05-40centimeter per minute) N₂ sccm None  20-90 BCl₃ sccm None  20-90 Ar sccm 10-60  10-60 O₂ sccm  50-400  50-400

The reactive chemistry combination is carefully chosen in a manner thatit reacts differently to the SiGe interfacial layer 66 l and the activelayer 24 (i.e., the doped source-drain epitaxial silicon layer) causinga variable net performance. In other words, the reactive chemistrycombination is optimized to achieve an infinite selectivity between SiGeand silicon by shifting the net performance to an etching performance ofthe SiGe interfacial layer 66 l, and to a forming performance of theetch passivation film 48 over the active layer 24. When the SiGeinterfacial layers 66 l are exposed to the reactive chemistrycombination, the etching rate of the F and Cl radicals is faster thanthe forming rate of the BN and BCl_(x), such that the net performance isthe etching performance leading to the removal of the SiGe interfaciallayers 66 l, as illustrated in FIG. 8 (Step 212). A net etching speed ofthe SiGe interfacial layers 66 l may be between 10 Å/min and 300 Å/min.

Once the SiGe interfacial layers 66 l are completely removed, the activelayers 24 are exposed to the reactive chemistry combination. For theactive layers 24, the etching rate of the F and Cl radicals is slowerthan the forming rate of the BN and BCl_(x), such that the netperformance is the forming performance of the etch passivation film 48over each active layer 24, as illustrated in FIG. 9 (Step 214).Therefore, each active layer 24 is not etched at all or only minimallyetched at a top surface. Accordingly, superior etching selectivity isachieved between the SiGe interfacial layers 66 l and the active layers24. In a more general way, the superior etching selectivity can beachieved between SiGe material and doped silicon material by utilizing aspecial reactive chemistry combination (e.g., a gas combination of SF₆,N₂, and BCl₃). A net forming speed of the etch passivation film 48 maybe between 1 Å/min and 20 Å/min. In one embodiment, the net formingspeed of the etch passivation film 48 may be much slower than the netetching speed of the SiGe interfacial layer 66 l.

During the SiGe etching step (Step 212) and the passivation film formingstep (Step 214), the isolation sections 44 are not etched by the mixedgas flow. In the mixed gas flow, SF₆ may have a flow rate of 5-60 sccm,N₂ may have a flow rate of 20-90 sccm, BCl₃ may have a flow rate of20-90 sccm, O₂ may have a flow rate of 50-400 sccm, and Ar may have aflow rate of 10-60 sccm. By adjusting the flow ratio of respective gasflows, different etching/forming rates and selectivity can be achievedbetween the SiGe interfacial layers 66 l and the active layers 24. Inone embodiment, the reactive chemistry combination and the flow ratiosof these reactive gas components may remain constant during the SiGeetching step (Step 212) and the passivation film forming step (Step214).

Next, the device passivation layers 15 are formed over the etchpassivation film 48, as illustrated in FIGS. 10A and 10B (Step 216). Thedevice passivation layers 15 continuously cover exposed surfaces withineach opening 46 and the top surface of each isolation section 44. Asshown in FIG. 10A, the first device passivation layer 15-1 is firstlyapplied continuously over the exposed surfaces within each opening 46and the top surface of each isolation section 44. The first devicepassivation layer 15-1 is in contact with the passivation layer 48 andalways covers each active layer 24. The first device passivation layer15-1 may be formed of silicon dioxide by a plasma enhanced depositionprocess, an anodic oxidation process, an ozone-based oxidation process,or a number of other proper techniques. The first device passivationlayer 15-1 is configured to terminate the surface bonds at the topsurface of the active layer 24, which may be responsible for unwantedleakage.

As shown in FIG. 10B, the second device passivation layer 15-2 is thenapplied directly over the first device passivation layer 15-1. Thesecond device passivation layer 15-2 also covers each active layer 24,side surfaces of each isolation section 44 within each opening 46, andthe top surface of each isolation section 44. Herein, the second devicepassivation layer 15-2 may be formed of silicon nitride and isconfigured to provide an excellent barrier to moisture and impurities,which could diffuse into the channel 32 of the active layer 24 and causereliability concerns in the device. The second device passivation layer15-2 may be formed by a chemical vapor deposition system such as aplasma enhanced chemical vapor deposition (PECVD) system, or an atomiclayer deposition (ALD) system.

After the device passivation layers are formed, the first mold compound16 is applied over the device passivation layers 15 to provide a molddevice wafer 78, as illustrated in FIG. 11 (Step 218). The mold devicewafer 78 includes a number of the mold device dies 12, each of whichincludes the device region 14, a portion of the device passivationlayers 15, and a portion of the first mold compound 16. Herein, thefirst mold compound 16 fills each opening 46, fully covers the devicepassivation layers 15, and is in contact with the second devicepassivation layer 15-2.

The first mold compound 16 may be applied by various procedures, such ascompression molding, sheet molding, overmolding, transfer molding, damfill encapsulation, and screen print encapsulation. The first moldcompound 16 may have a superior thermal conductivity greater than 1W/m·K or greater than 10 W/m·K, and may have a dielectric constant lessthan 8 or between 3 and 5. During the molding process of the first moldcompound 16, the temporary carrier 72 provides mechanical strength andrigidity to the etched wafer 76. A curing process (not shown) isfollowed to harden the first mold compound 16. The curing temperature isbetween 100° C. and 320° C. depending on which material is used as thefirst mold compound 16. After the curing process, the first moldcompound 16 may be thinned and/or planarized (not shown).

The temporary carrier 72 is then debonded from the mold device wafer 78,and the bonding layer 74 is cleaned from the mold device wafer 78, asillustrated in FIG. 12 (Step 220). A number of debonding processes andcleaning processes may be applied depending on the nature of thetemporary carrier 72 and the bonding layer 74 chosen in the earliersteps. For instance, the temporary carrier 72 may be mechanicallydebonded using a lateral blade process with the stack heated to a propertemperature. Other suitable processes involve radiation of UV lightthrough the temporary carrier 72 if it is formed of a transparentmaterial, or chemical debonding using a proper solvent. The bondinglayer 74 may be eliminated by wet or dry etching processes, such asproprietary solvents and plasma washing. After the debonding andcleaning process, the bottom portions of certain ones of the connectinglayers 50, which may be functioned as input/output (I/O) ports of themold device die 12, are exposed through the dielectric layers 52 at thebottom surface of each BEOL portion 22. As such, each mold device die 12in the mold device wafer 78 may be electrically verified to be workingproperly at this point.

With reference to FIGS. 13A-13C, the multilayer redistribution structure18 is formed underneath the mold device wafer 78 according to oneembodiment of the present disclosure (Step 222). Although theredistribution steps are illustrated in a series, the redistributionsteps are not necessarily order dependent. Some steps may be done in adifferent order than that presented. Further, redistribution stepswithin the scope of this disclosure may include fewer or more steps thanthose illustrated in FIGS. 13A-13C.

A number of the redistribution interconnections 54 are firstly formedunderneath each BEOL portion 22, as illustrated in FIG. 13A. Eachredistribution interconnection 54 is electrically coupled to the exposedbottom portion of the corresponding connecting layer 50 within the BEOLportion 22 and may extend over the bottom surface of the BEOL portion22. The connections between the redistribution interconnections 54 andthe connecting layers 50 are solder-free. The dielectric pattern 56 isthen formed underneath each BEOL portion 22 to partially encapsulateeach redistribution interconnection 54, as illustrated in FIG. 13B. Assuch, the bottom portion of each redistribution interconnection 54 isexposed through the dielectric pattern 56. In different applications,there may be extra redistribution interconnections (not shown)electrically coupled to the redistribution interconnection 54 throughthe dielectric pattern 56, and extra dielectric patterns (not shown)formed underneath the dielectric pattern 56, such that a bottom portionof each extra redistribution interconnection is exposed.

Next, a number of the bump structures 58 are formed to complete themultilayer redistribution structure 18 and provide a wafer-level fan-out(WLFO) package 80, as illustrated in FIG. 13C. Each bump structure 58 isformed at the bottom of the multilayer redistribution structure 18 andelectrically coupled to an exposed bottom portion of the correspondingredistribution interconnection 54 through the dielectric pattern 56.Consequently, the redistribution interconnections 54 are configured toconnect the bump structures 58 to certain ones of the connecting layer50 in the BEOL portion 22, which are electrically connected to the FEOLportion 20. As such, the bump structures 58 are electrically connectedto the FEOL portion 20 via corresponding redistribution interconnections54 and corresponding connecting layers 50. In addition, the bumpstructures 58 are separate from each other and extend underneath thedielectric pattern 56.

The multilayer redistribution structure 18 may be free of glass fiber orglass-free. Herein, the glass fiber refers to individual glass strandstwisted to become a larger grouping. These glass strands may then bewoven into a fabric. The redistribution interconnections 54 may beformed of copper or other suitable metals, the dielectric pattern 56 maybe formed of BCB, polyimide, or other dielectric materials, and the bumpstructures 58 may be solder balls or copper pillars. The multilayerredistribution structure 18 has a thickness between 2 μm and 300 μm.FIG. 14 shows a final step to singulate the WLFO package 80 intoindividual RF devices 10 (Step 224). The singulating step may beprovided by a probing and dicing process at certain isolation sections44.

It is contemplated that any of the foregoing aspects, and/or variousseparate aspects and features as described herein, may be combined foradditional advantage. Any of the various embodiments as disclosed hereinmay be combined with one or more other disclosed embodiments unlessindicated to the contrary herein.

Those skilled in the art will recognize improvements and modificationsto the preferred embodiments of the present disclosure. All suchimprovements and modifications are considered within the scope of theconcepts disclosed herein and the claims that follow.

What is claimed is:
 1. A radio frequency (RF) device comprising: a molddevice die comprising a device region, an etch passivation film, and afirst mold compound, wherein: the device region includes afront-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portionunderneath the FEOL portion, wherein the FEOL portion comprises anactive layer and isolation sections, which surround the active layer andextend vertically beyond a top surface of the active layer to define anopening within the isolation sections and over the active layer; theetch passivation film resides over the top surface of the active layerand within the opening, wherein the etch passivation film is formed ofboron nitride (BN) and boron chloride (BCl_(x), x=0-3); and the firstmold compound resides over the etch passivation film to fill theopening; and a multilayer redistribution structure formed underneath theBEOL portion of the mold device die, wherein the multilayerredistribution structure comprises a plurality of bump structures, whichare on a bottom surface of the multilayer redistribution structure andelectrically coupled to the FEOL portion of the mold device die.
 2. TheRF device of claim 1 wherein: the BEOL portion comprises connectinglayers; the FEOL portion further comprises a contact layer, wherein theactive layer and the isolation sections reside over the contact layer,and the BEOL portion resides underneath the contact layer; and themultilayer redistribution structure further comprises redistributioninterconnections, wherein the plurality of bump structures iselectrically coupled to the FEOL portion of the mold device die via theredistribution interconnections within the multilayer redistributionstructure and the connecting layers within the BEOL portion.
 3. The RFdevice of claim 2 wherein the FEOL portion is configured to provide aswitch field-effect transistor (FET).
 4. The RF device of claim 3wherein the active layer includes a source, a drain, and a channel ofthe FET, while the contact layer includes a gate structure of the FET,the gate structure extending horizontally underneath the channel.
 5. TheRF device of claim 1 wherein the first mold compound has a thermalconductivity greater than 1 W/m·K.
 6. The RF device of claim 5 whereinthe first mold compound has a thermal conductivity greater than 10W/m·K.
 7. The RF device of claim 1 wherein the first mold compound has adielectric constant less than
 8. 8. The RF device of claim 7 wherein thefirst mold compound has a dielectric constant between 3 and
 5. 9. The RFdevice of claim 1 wherein a portion of the first mold compound residesover the isolation sections.
 10. The RF device of claim 1 furthercomprising one or more device passivation layers, wherein: the one ormore device passivation layers extend over an entire backside of thedevice region, such that the one or more device passivation layerscontinuously cover the etch passivation film and side surfaces of theisolation sections within the opening, and top surfaces of the isolationsections; and the first mold compound resides over the one or moredevice passivation layers to fill the opening.
 11. The RF device ofclaim 10 wherein the one or more device passivation layers are incontact with a top surface of the etch passivation film.
 12. The RFdevice of claim 10 wherein the first mold compound is in contact with atop surface of the one or more device passivation layers.
 13. The RFdevice of claim 10 wherein the one or more device passivation layers areformed of silicon composites.
 14. The RF device of claim 13 wherein theone or more device passivation layers includes a first devicepassivation layer and a second device passivation layer, wherein: thefirst device passivation layer extends over the entire backside of thedevice region, such that the first device passivation layer continuouslycovers the etch passivation film and the side surfaces of the isolationsections within the opening, and the top surfaces of the isolationsections; the second device passivation layer resides over the firstdevice passivation layer, wherein the first device passivation layer andthe second device passivation layer are formed from different siliconcomposites; and the first mold compound resides over the second devicepassivation layer to fill the opening.
 15. The RF device of claim 14wherein: the first device passivation layer is configured to terminatesurface bonds at the top surface of the active layer; and the seconddevice passivation layer is configured to provide a barrier to moistureand impurities attempting to diffuse into the active layer.
 16. The RFdevice of claim 15 wherein: the first device passivation layer is formedof silicon dioxide; and the second device passivation layer is formed ofsilicon nitride.
 17. The RF device of claim 1 wherein the isolationsections are formed of silicon dioxide.
 18. The RF device of claim 1wherein the FEOL portion is configured to provide at least one of aswitch FET, a diode, a capacitor, a resistor, or an inductor.
 19. The RFdevice of claim 1 wherein the etch passivation film is in contact withthe top surface of the active layer.
 20. The RF device of claim 1wherein no silicon crystal exists between the first mold compound andthe top surface of the active layer, wherein the silicon crystal has nonitrogen or oxygen content.